`timescale 1 ps / 1 ps
module mult_8x16(
	input	wire		CLK,
	input	wire	[7:0]	A,
	input	wire	[15:0]	B,
	output	reg	[23:0]	P
	);

wire	[23:0]	pp;

	lpm_mult	lpm_mult_component (
				.dataa (A),
				.datab (B),
				.result (pp),
				.aclr (1'b0),
				.sclr (1'b0),
				.clken (1'b1),
				.clock (1'b0),
				.sum (1'b0));
	defparam
		lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
		lpm_mult_component.lpm_representation = "UNSIGNED",
		lpm_mult_component.lpm_type = "LPM_MULT",
		lpm_mult_component.lpm_widtha = 8,
		lpm_mult_component.lpm_widthb = 16,
		lpm_mult_component.lpm_widthp = 24;

always @(posedge CLK)
	P <= pp;

endmodule
